1. Field of the invention
The present invention relates to a CRC code generation circuit, a code error detection circuit and a CRC circuit used in CD-ROM MODE 1 or CD-ROM MODE 2, for example, in the field of communication or storage media. More specifically, the present invention relates to a CRC code generation circuit for generating a CRC (Cyclic Redundancy Check) code or an EDC (Error Detection Code) code (hereinafter, these codes are referred to generally as an error detection code (CRC code)), a code error detection circuit for detecting an error using the CRC code, and a CRC circuit which functions both as a CRC code generation circuit and a code error detection circuit.
2. Description of the prior art
A CRC code word used in CD-ROM MODE 1 consists of a fixed pattern for synchronization, data following this pattern, and an error detection code (CRC code) which is added to the fixed pattern and the data.
Japanese Patent publication No. 4-81896 discloses a decode error detection circuit for detecting a code error, in which the CRC code word is regarded as one block. The error detection circuit disclosed in this publication comprises a dividing circuit consisting of a shift register to which data in a CRC code word and CRC code are input, a NOR circuit which receives an output from the dividing circuit and outputs a signal indicating "no error" when all the bits in the result from the dividing circuit are "0", and a signal indicating "error" when even one bit is "1", and an initial setting means for setting the initial state of a register, constituting the dividing circuit, to the same state as when the fixed pattern of the CRC code is input sequentially.